As Si technology continues to scale following Moore's law, multi-core and many-core processors are going to be common in high performance server market segments. These processors need increased processor-to-processor (or I/O hub) and processor-to-memory bandwidth to make optimal use of the huge computing power of the multi- or many-cores. The Input/Output (I/O) bandwidth (given by number of I/O pins times data flow rate) can be increased by either increasing the number of pins or data rate or both. Both of these options for increasing bandwidth usually tend to drive up the cost. Increasing number of I/O pins causes Si, package, and socket size growth. A larger socket takes more board space and in certain cases also increases the board layer count. Increasing data rate to improve bandwidth on the other hand is confronted by technological challenges and the corresponding cost impact. Signal integrity (SI) issues due to signal reflections and crosstalk associated with package, socket, and board vertical transitions impose severe constraints on the maximum achievable signaling speed in an interconnect system. Even though various known techniques such as voiding of package planes around plated-through-hole (PTH) vias, decreasing the size of the PTHs (and in some cases eliminating PTHs in package substrate), back-drilling of board vias, and crosstalk reduction by placing sufficient ground pins in the socket/connector exist to mitigate some of the these SI issues, cost and high-volume manufacturing (HVM) reliability limit the extent of applicability of these methods for products.